
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity modulo_pwm_nios is

  port (

    -- Avalon clock Interface
    csi_clk  : in std_logic;
    -- Reset
    reset_n :    std_logic;

    -- Avalon MM Slave - Interface
    avs_read       : in  std_logic;
    avs_address    : in  std_logic_vector(1 downto 0);
    avs_chipselect : in  std_logic;
    avs_write      : in  std_logic;
    avs_writedata  : in  std_logic_vector(31 downto 0);
    avs_readdata   : out std_logic_vector(31 downto 0);

    -- Conduit Interface
    coe_PWM : out std_logic
    );
end entity;

architecture RTL of modulo_pwm_nios is


  -- PWm Module Signals
  signal HABILITA, INV_PWM, HAB_SAIDAn, RSTn : std_logic;
  signal TAXA_next, TAXA_reg                 : std_logic_vector (7 downto 0);
  signal PRESCALER_next, PRESCALER_reg       : std_logic_vector (7 downto 0);
  signal PWM_next, PWM_reg                   : std_logic;
  signal control_reg, control_next           : std_logic_vector(3 downto 0);
  signal reset_pwm                           : std_logic;



begin

--=======================================================
-- Registers
--=======================================================

  regs : process (reset_n, csi_clk)
  begin
    if (reset_n = '0') then
      TAXA_reg      <= (others => '0');
      PRESCALER_reg <= (others => '0');
      control_reg   <= (others => '0');
      PWM_reg       <= '0';
    elsif rising_edge(csi_clk) then
      TAXA_reg      <= taxa_next;
      PRESCALER_reg <= PRESCALER_next;
      control_reg   <= control_next;
      PWM_reg       <= PWM_next;
    end if;
  end process;

--=======================================================
-- PWM MODULE
--=======================================================

  modulo_pwm_1 : entity work.modulo_pwm
    port map (
      CLK        => csi_clk,
      RSTn       => reset_pwm,
      HABILITA   => HABILITA,
      INV_PWM    => INV_PWM,
      HAB_SAIDAn => HAB_SAIDAn,
      
	  TAXA       => TAXA_reg,
      PRESCALER  => PRESCALER_reg,
      PWM        => PWM_next);

reset_pwm <= (RSTn or reset_n);
--=======================================================
-- next state logic
--=======================================================

  control_next <= avs_writedata(3 downto 0) when ((avs_write = '1') and (avs_chipselect = '1') and (avs_address = "00"))
                  else control_reg;
  TAXA_next <= avs_writedata(7 downto 0) when ((avs_write = '1') and (avs_chipselect = '1') and (avs_address = "01"))
               else TAXA_reg;
  PRESCALER_next <= avs_writedata(7 downto 0) when ((avs_write = '1') and (avs_chipselect = '1') and (avs_address = "10"))
                    else PRESCALER_reg;
  avs_readdata(3 downto 0) <= control_reg when ((avs_read = '1') and (avs_chipselect = '1'))
                             else "0000";
  avs_readdata(31 downto 4) <= (others => '0');


  RSTn       <= control_reg(0);
  HABILITA   <= control_reg(1);
  INV_PWM    <= control_reg(2);
  HAB_SAIDAn <= control_reg(3);
  coe_PWM    <= PWM_reg;


end architecture;
